1. Field of the Invention
The present invention relates to analog-to-digital (A/D) converter circuits and more specifically to the reduction of aperture distortion in parallel circuits of this type by conditioning of the sample-and-hold clocks.
2. Description of the Related Art
FIG. 1a shows a typical block diagram for a two channel parallel A/D converter circuit. In this circuit, the analog input signal is directed along two parallel data paths, each consisting of a sample-and-hold (S/H) circuit in series with an analog-to-digital converter circuit; i.e., one path comprised of S/H 10 in series with A/D 12 and the other path comprised of S/H 11 in series with A/D 13. The two paths are then coupled to a digital multiplexer 14 where the signals are recombined to provide the digital output. The analog input signal is sampled in an odd-even fashion within the two signal paths by means of sample-and-hold clocks, Clock A and Clock B.
FIG. 1b shows the timing diagram for the typical two channel A/D converter circuit of FIG. 1a. Clock A is the clock for. one of the parallel channel sample-and-hold circuits and Clock B is the clock for the other parallel channel sample-and-hold circuit, with Clock A and Clock B being complementary. Typically, the analog signal Vin is sampled on the trailing or negative edge of these clock pulses, as shown, alternating between Clock A and Clock B. Ideally, the high-to-low sampling edge of the clocks should be exactly 1/T apart in time, where T is the period of the clock pulse. However, in practice this is normally not the case due to the delay mismatch of the circuit parameters which can result in the presence of intermodulation tones in the sampled signal, given by       fin    ±          fs      2        ;
where fs is the sampling frequency.
Typically, in attempting to minimize this circuit mismatch, a method of generating the complementary sample-and-hold clock signals from a single master clock, as shown in FIG. 2, is used. Here, the complementary Clock A and Clock B signals are generated, by means of a divide-by-2 flip-flop 20 circuit, from a master clock signal. However, the drawback of this simple approach is that of signal delay, caused by component mismatching in the divide-by-2 flip-flop 20, which can result in significant delay between Clock A and Clock B, resulting in aperture distortion in the A/D converter.
One approach for improving the delay mismatch in the above circuit is to recombine the generated complementary clocks with the master clock by means of gating the two together, as shown in FIG. 3, in order to remove some of the delay mismatch. In operation, the circuit generates two complementary sample-and-hold clocks, Clock A and Clock B, from a single master clock signal. The circuit is comprised of a flip-flop (F/F) 30 and two transmission gates (gated switches) 31-32. The complementary outputs, Q and {overscore (Q)}, of flip-flop 30 are connected, respectively, to the inputs of the two gated switches 31-32. A master clock (Clk) is connected to the input of flip-flop 30 and to the gates of switches 31-32. Finally, the outputs of the gated switches 31-32 provide the conditioned Clock A and Clock B sample-and-hold signals. In this circuit, the delay mismatch introduced by flip-flop 30 is effectively removed by gating the two flip-flop 30 output signals, Q and {overscore (Q)}, again with the master clock by means of the two gated switches 31-32. However, there is some amount of delay mismatch introduced between the two signals by the two transmission gates 31-32 themselves, although this mismatch can be minimized and somewhat controlled by matching the threshold of the gates and by maintaining the overall circuit time constant at a minimum. These factors can be addressed during the design of the integrated circuit.
The new approach of this invention addresses the drawbacks of the above circuits and significantly improves the aperture distortion problem found in many typical parallel A/D converter circuits.
A method and circuit for reducing the aperture distortion in parallel A/D converters by improving the delay mismatch in the sample-and-hold stages of the circuit is disclosed. The technique involves generating two complementary sample-and-hold signals, Q and {overscore (Q)}, from a single master clock and then gating them again with the original master clock in a random fashion to significantly reduce delay mismatch between them, thereby improving the aperture distortion in the circuit. It is the random nature of the approach that constitutes this invention.
In this approach, the sample-and-hold circuit""s delay mismatch is further reduced by providing a plurality of randomly selected parallel paths for gating the generated complementary signals, Q and {overscore (Q)}, with the master clock. These parallel paths each consist of a randomly selected switch in series with a master clock switch. This technique tends to convert any systematic aperture mismatch between the two generated complementary clocks, Clock A and Clock B, into random noise which is spread over a wide band of frequencies.
High speed parallel A/D converters utilizing the sample-and-hold aperture distortion reduction techniques of this invention are used in, but are not limited to, such applications as:
1) video signal processing,
2) video bandwidth compression,
3) digital video transmission/reception,
4) digital audio processing,
5) digital image enhancement,
6) radar signal analysis, and
7) others.